Description:
Job Role: Hardware Engineer Mid Location: San Jose, CA (5 Days Onsite) Duration: 12 months, possible extension Job Description: Technical: Being a member of design team who oversees full chip STA and works with physical design and DFT teams to close fullchip timing in multiple timing modes.Option to also do block level RTL design or block or top-level IP integration.Helping develops efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block
Jul 10, 2025;
from:
dice.com