Description:
Senior ASIC Engineer, Static Timing Analysis -AMDJP00004058 Location: San Jose, CA- Onsite. Alternate location: Colorado office - 3100 Logic Dr, Longmont Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff & the expertise we need with these tools (DC/PT). Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA tool compe
Jul 21, 2025;
from:
dice.com