Synthesis & Low power Design

Description:

Own and optimize RTL-to-GDSII implementation flows using Synopsys Fusion Compiler, including synthesis, placement, routing, and signoff.Develop and maintain RTLA-based power estimation and optimization flows, integrating with PrimePower RTL and design environments.Collaborate with RTL and physical design teams to define timing constraints, UPF-based power intent, and switching activity annotations for accurate power analysis.Drive methodology improvements for early RTL power estimation, scenario