Description:
Role: Design Verification Engineer (System Verilog/UVM) Location: Markham, ON (3 days Onsite) Contract Job Description: We are seeking a motivated Design Verification Engineer with 3 years of relevant experience in System Verilog and UVM to join our dynamic team. You will play a critical role in verifying digital designs through rigorous methodologies and advanced toolsets. Responsibilities: Develop testbenches and verification environments using System Verilog and UVM for IP/subsystem/SoC lev
Jul 29, 2025;
from:
dice.com