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Senior Design Verification Engineer

Cynet Systems
Ontario Full-day Full-time

Description:

Job Description: Responsibilities: Develop/Maintain tests for functional verification with UVM verification at the subsystem level. Build testbench components to support the next generation IP. Maintain or improve current test libraries to support IP level testing. Technically lead IPs in Control Fabric. Have exposure to AXI protocol and Bootcode Verification. Provide technical support to other teams. Preferred Experience: 5+ years' experience required. Good at C/C++. Good at SV and UVM. Good sc
Aug 14, 2025;   from: dice.com

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