Description:
Job Description ONSITE 5 days - San Jose, CA or Austin, TX MUST Design Verification experience: 3+ year experience if in Austin; 5+ year experience if in San Jose, CA SystemVerilog (developed test benches and test cases) UVM Debug Verification test plans (develop and execute) Essential Skills & Qualifications: SystemVerilog: proficient in SystemVerilog for developing testbenches and test cases, UVM: solid understanding and practical experience with UVM (Universal Verification Methodology) De
Aug 20, 2025;
from:
dice.com