Description:
Title: Analog Layout Engineer. Location: Cupertino, CA or Austin, TX. Duration: 12+ Months Contract Position. Looking for 4 to 8 Years Experience or more. Technical Skills: Technology Nodes: Experience with advanced semiconductor process technologies including 7nm, 5nm, and 16nm nodesHigh-Speed Design: Proficient in High-Speed Layout and design methodologiesMemory Interfaces: Familiar with DDR (Double Data Rate) memory technologiesMemory Design: Experience in Memory Layout and Design (possibly
Sep 6, 2025;
from:
dice.com