Description:
Title: Analog/Mixed Signal IC layout Engineer Location: Alameda, CA (onsite) Duration: 3+ months contract 4-5 years experience in Cadence layout (Design: Virtuoso Verification: PVS ) and Calibre verification (ERC, DRC, LVS)Experience in custom Analog and Digital Layout.Demonstrated success in chip tapeout process.Experience in DFM hierarchical layout construction.Experience in floorplan, power plan and signal Planning for Mixed Signal chips.Must understand techniques for managing layout depende
Sep 7, 2025;
from:
dice.com