Physical Design Engineer opportunity to work for a Hardware company focused on accelerating training and inference performance for large AI models

Description:

Full Time opportunity in Saratoga, CA Key Responsibilities Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. Proficiency in Synthesis design constraints (SDC). Design and Architect Top Level and block Level Floor planning of the entire SoC. Sound Proficiency in either Innovus or Synopsys Fusion Compiler required. Proficiency in synthesis, Floor planning Power Planning and Timing closur