Description:
Job Title: Senior Engineer Location: San Jose, CA (5 days to offce weekly) Contract: 6+ Months Job Description Design Verification expertise in System Verilog /UVM Unit/Module level Verification Experience in test planning and debugging complex designs Full silicon design lifecycle experience Strong background in developing UVM Testbenches from scratch Deep understanding of Computer Architecture Test Planning, Coverage, Bring up Phase, Design Freeze and ECO Phase Experience with caches and mem
Sep 19, 2025;
from:
dice.com