Description:
Position Title: Power Optimization Engineer Location: San Jose, CA (Hybrid) Clearance Requirements: None Position Status: Contract (W2 only) Pay Rate: $90 $130/hr Position Description: We are seeking a Power Optimization Engineer to support advanced low-power ASIC development. In this role, you'll drive RTL-level power optimization initiatives across IP design teams, working with state-of-the-art tools and methodologies to deliver energy-efficient silicon. This hybrid position is based in San Jo
Sep 25, 2025;
from:
dice.com