Description:
Job Description: We are seeking a highly skilled and meticulous SystemVerilog/UVM Design Verification Test Engineer to play a crucial role in validating our complex System-on-Chip (SOC) and Integrated Circuit (IC) designs. This role requires expert-level proficiency in SystemVerilog and UVM, a strong understanding of processor architectures, and high-speed protocols. Responsibilities: Architect, develop, and maintain advanced verification environments (Testbenches) using UVM and SystemVerilog
Oct 14, 2025;
from:
dice.com