Description:
Implementation DFT structure, including Tessent EDT scan chains, Memory BIST and Logic BIST to ensure high test coverage and low test time Generate Scan and MBIST test patterns using ATPG tools Collaborate with the design team to ensure integration of DFT features Conduct gate-level simulation(GLS) with timing annotation and power and ground connection. Debug simulation failure with waveform viewer In-depth knowledge of MBIST algorithm Strong understanding of SOC power structure and low power de
Oct 14, 2025;
from:
dice.com