Description:
Job Title FPGA RTL design and Board validation Location: Santa Clara, CA (Onsite) Job Type- Fulltime Note- Email: Job Description: We are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years of experience in RTL design, IP design and development, and FPGA validation and testing. The ideal candidate will have a strong background in design debugging and a deep familiarity with Quartus tools. This role requires a detail oriented individual who can effectively contribute to softw
Nov 10, 2025;
from:
dice.com