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FPGA/RTL Design Engineer

Wise Equation Solutions Inc.
San Jose Full-day Full-time

Description:

Design & Implementation: Develop RTL code (Verilog, VHDL, SystemVerilog) for FPGA and digital circuits, integrating IP and system software. Simulation & Debugging: Perform functional simulation, debug FPGA designs, and resolve design issues. Validation & Testing: Create unit tests, example designs, and demos; ensure readiness of feature releases. Technical Enablement: Develop user guides, application notes, and training materials for customers. Customer Support: Respond to technical inquiries, r
Nov 18, 2025;   from: dice.com
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