Senior FPGA Engineer

Description:

Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands-on experience with UVM (Universal Verification Methodology)Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)Experience with code and functional coverage analysisProficient in debugging and problem-solvingScripting experience in Python or PerlKnowledge of Verilog and/or VH