Description:
Mixed Signal Model Verification Engineer San Jose, CA (Hybrid) 3 + Months $90-95/HR Goal: Verify SystemVerilog (logic/real number) behavioral models against custom circuit schematics using formal equivalence checking and co-simulation. Requirements: SystemVerilog Modeling: Extensive experience with SystemVerilog, including real number modeling. Verification Flow: Strong understanding of HDL/SPICE co-simulations. Circuit Expertise: Strong background in analog integrated circuit design and read
Dec 5, 2025;
from:
dice.com