Description:
Role: Design Verification Engineer Location: San Jose CA/ Irvine CA / San Diego CA Job Description:Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simula
Jan 6, 2026;
from:
dice.com