Description:
We are seeking a highly experienced ASIC Power Engineer to support power analysis and optimization for next-generation AR/VR silicon products. This role focuses on power, performance, and area (PPA) optimization across RTL and netlist levels, working closely with synthesis, physical design, and verification teams. The ideal candidate has strong expertise in low-power methodologies, ASIC tool flows, and scripting for data analysis, with exposure to Machine Learning driven products being a plus. K
Jan 12, 2026;
from:
dice.com