Description:
Preferred Qualifications: Experience in analog/custom layout design in advanced CMOS process(2+ years FinFet experience must)Expertise in Cadence VLE/VXL,PVS, Assura and Calibre DRC/ LVS is a must.Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Comparator, DDR blocks etc.,Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, c
Jan 26, 2026;
from:
dice.com