Description:
FULLY REMOTE - OPEN TO CANADIAN CITIZENS Key Responsibilities: Develop and maintain SystemVerilog/UVM-based testbenches for complex digital designs.Create and execute detailed test plans covering directed and constrained-random scenarios.Apply Object-Oriented Design principles to build scalable and reusable verification components.Analyze and improve code coverage metrics to ensure thorough verification.Write and maintain scripts (e.g., Python, Perl, Tcl) to automate verification flows and data
Jan 29, 2026;
from:
dice.com