Description:
DFT Lead Location : San Jose ,CA or Chandler, Arizona ( Hybrid Work) Long Term Responsibilities Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost and DFT integration requirements are met at the block and full chip level. Define, implement and validate DFT features at the FPGA full chip and sub-systems level. Collaborate closely with cross functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static
Feb 2, 2026;
from:
dice.com