Description:
Job Title: Design Verification Engineer Location: CA Experience Level: 10+ Years Job Description: We are seeking a skilled Design Verification Engineer with strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ideal candidate will have hands-on experience in developing, updating, and debugging verification testbenches, with the ability to integrate Verification IPs (VIPs) or Design IPs into the verification environment. Responsibilities: Develop, enhance, and debug
Feb 3, 2026;
from:
dice.com