Description:
Position: PCIe Validation Engineer Location: San Diego, CA Exp: 5-8 years PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, Multimeter, Logic & Power Analyzer, BERTS C/C++, Python, Perl, Windows, Linux Take lead responsibility for validating PCIe and its subsystems on multiple SoC platforms.Define comprehensive test plans and execute tests covering memory training procedures, performance benchmarks, stress scenarios, timing margin analysis, and overall reliability.Collaborate with design and firm
Feb 11, 2026;
from:
dice.com