Description:
Position: SOC Post Silicon Validation Engineer Exp: 10+ years Location: San Jose, CA What Youll Be Doing / Key Responsibilities: Lead the development and execution of bring-up and silicon validation test plans for the SoC. Perform validation of SoC peripherals, including LPDDRx, PCIe, I2C, and qSPI. Manage and oversee all phases of the validation lifecycle, from initial bring-up to production release. Collaborate closely with cross-functional hardware and software teams to design and implement
Feb 11, 2026;
from:
dice.com