Description:
Role: Senior/Staff VLSI Engineer Ethernet FEC DV Duration: 12+ Months Location: San Jose, CA || Onsite Role Job Description-: We are seeking a highly skilled and motivated VLSI Design Verification Engineer with deep expertise in Forward Error Correction (FEC) and Ethernet protocols. In this role, you will own the verification of advanced FEC IP cores (RS-FEC, KR/KP4, or next-gen) within high-speed Ethernet controllers (25G/50G/100G/200G/400G+). You will develop sophisticated UVM environments, d
Feb 26, 2026;
from:
dice.com