Description: ASIC Engineer (Design Verification) Bay Area, CA or Austin, ... level verification. Develop functional tests based on verification test plan. Drive Design Verification to ...
5 days ago
Description: Title: Infra Silicon Physical Design Engineer Location: Bay Area, CA/Austin, ... experience performing timing and physical verification closure on 5nm FinFET TSMC ... experience with block level physical design (Floor planning to GDSII) - Experience ...
5 days ago