Description: Role: RTL Design Engineer Location: Santa Clara, CA ... -on experience in digital design at the RTL level using Verilog/SystemVerilog ... . Experience in designing and implementing RTL from scratch. Proficiency in applying ...
17 days ago
... Description: We are looking for a Senior FoundationDB Engineer - Location: Pasadena, CA ... Contract Position. Job Title: Senior FoundationDB Engineer Location: Pasadena, ... seeking a highly skilled Senior FoundationDB Engineer to design, implement, and optimize ...
3 days ago
... : Strong knowledge of System-Verilog RTL coding, including state machines, adders ... logic. Solid understanding of digital design for mixed-signal control loops ...
17 days ago