... EngineerIntroduction:An experienced Signal Integrity Engineer with at least 5 years of ... interface development and validation. The engineer will be working on cutting ...
a day ago
Description: Preferred Qualifications: Experience in analog/custom layout design in advanced CMOS process(2+ years FinFet experience must)Expertise in Cadence VLE/VXL,PVS, Assura and Calibre DRC/ LVS is a must.Should have hands on experience of Critical ...
18 days ago