Description: Role: Silicon Design Package Engineer Location: Hybrid (Santa Clara, CA ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ...
25 days ago
... , Full Time / Permanent Role Role: Design Verification Engineer Location : Sunnyvale CA / Austin ...
4 days ago
Description: Role: Design Verification Engineer Location: San Jose CA/ Irvine ...
17 days ago
Description: Job Title:DesignVerificationEngineerLocation:San Diego, CAExperience Level: 7+ YearsJob Description:We are seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ...
8 days ago
... Medical Device Quality Engineer / Senior Sustaining Quality Engineer Needed for Growing Medical ... for a talented Senior Design Quality Engineer / Senior Supplier Quality Engineer! Why join us ...
9 days ago
... Medical Device Quality Engineer / Senior Sustaining Quality Engineer Needed for Growing Medical ... for a talented Senior Design Quality Engineer / Senior Supplier Quality Engineer! Why join us ...
24 days ago
... Power Engineer DUTIES ASIC Power Engineer to perform power analysis and optimizations in ... and SystemVerilog. RESPONSIBILITIES Perform PPA optimization with Fusion compiler. Perform RTL ...
11 days ago
... in the design, development, implementation, integration, testing, deployment, operation, optimization, administration, troubleshooting ... . Essential Job Functions: Conduct Research, Design, Fabrication and Integration of
3 days ago
... Description Thermal Design: Heatsink topology, vapor chambers, heat pipes, fin optimization; fan ...
11 days ago
... Software Engineer, you will be a key contributor to the design, development, and optimization ... . We are specifically looking for engineers with hands-on Erlang experience ...
2 days ago
Description: Role: ASIC Power Engineer Location: Sunnyvale, CA (Hybrid) DUTIES: ... ASIC Power Engineer to perform power analysis and optimizations in ASIC for ... and SystemVerilog. RESPONSIBILITIES: Perform PPA optimization with Fusion compiler. Perform RTL ...
11 days ago
... company building advanced analytics and optimization platforms for complex, large-scale ... . As a Senior Data Platform Engineer, you will design and scale the core ...
17 days ago
... a Senior DevOps Engineer to lead the deployment and optimization of OpenStack-based ...
7 days ago
... experienced Quality Engineer who thrives in regulated environments, drives process optimization, and ...
8 days ago
... : Job ID: 65213 Senior Server Engineer Location: 55 Trinity Avenue, Suite ... Senior Server Engineer (Contract) will lead engineering, troubleshooting, and optimization of enterprise ...
9 days ago
... 1) We're looking for an engineer with deep expertise in scientific ... -GPU training and GPU memory optimization
25 days ago
... complex challenges in machine learning, optimization, and distributed systems to power ...
6 days ago
... complex challenges in machine learning, optimization, and distributed systems to power ...
7 days ago
... pricing and incentives simulation and optimization. The role will provide an ...
7 days ago
... Do: Lead the development and optimization of state-of-the-art ...
8 days ago