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Jobs and careers temporary for principal verification engineer in California (13 jobs)

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  • InfiCare Technologies
  • Mountain View
Description: Title-FPGA Verification Engineer Location-Mountain View, CA Duration- ... -Onsite Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... in System Verilog and UVM verification methodology. Experience with industry-standard ...
14 days ago
Description: Medical Device Leader! Principal Quality Engineer Opportunity! This Jobot Consulting Job ...
a day ago
  • Pacific Consultancy Services
  • Mountain View
... Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite ... in System Verilog and UVM verification methodology. Experience with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS). ...
16 days ago
  • Pacific Consultancy Services
  • Mountain View
... Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite ... in System Verilog and UVM verification methodology. Experience with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS). ...
22 days ago
  • Siri Infosolutions Inc
  • Irvine
Description: Job Title: V&V Engineer/System Verification Engineer Location: Irvine CA (Onsite Position ...
7 days ago
  • Kainos Innovative Solutions Inc
  • Santa Clara
... in System Verilog and UVM verification methodologyExperience with Linux operating systemExperience ... with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps ...
20 days ago
  • SPECTRAFORCE TECHNOLOGIES Inc.
  • Santa Clara
... Engineer Location: Santa Clara, CA, 95051 Duration:12 Months Job Description: Principal ...
16 days ago
  • Judge Group, Inc.
  • Escondido
... Description: Job Title: Systems Safety Engineer Location: San Diego, CA About ... We are seeking a Senior Principal Systems Safety Engineer to join our team ...
20 days ago
  • OSI Engineering, Inc.
  • Cupertino
... outstanding Camera Image Quality Test Engineer who has a good understanding of ... and real world image quality verification to help deliver the best ...
17 days ago
  • Technical Link
  • San Jose
Description: As aLead Package Design Engineer, you will take ownership of ... for manufacturing, and sign-off verification. You will also , guiding best ...
22 days ago
  • Prospance Inc.
  • Palo Alto
... for a Staff level Embedded Software Engineer to join our team, focusing ... the software stack for Design Verification of PCBAs & ECUs (Electronic Component ...
23 days ago
  • BayOne Solutions
  • Palo Alto
... for a Staff level Embedded Software Engineer to join our team, focusing ... the software stack for Design Verification of PCBAs & ECUs (Electronic Component ...
23 days ago
  • Cygnus Professionals
  • Irvine
Description: 1.Good in SolidWorks (1 to 2 years) 2.Windchill Change management experience 3.Medical Device Product development 4.Validation & Verification (V&V) 5. Good in communication and interpersonal skills
22 days ago