Description: Title-FPGA Verification Engineer Location-Mountain View, CA Duration- ... -Onsite Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... in System Verilog and UVM verification methodology. Experience with industry-standard ...
12 days ago
... Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite ... in System Verilog and UVM verification methodology. Experience with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS). ...
15 days ago
... Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite ... in System Verilog and UVM verification methodology. Experience with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS). ...
20 days ago
Description: Job Title: V&V Engineer/System Verification Engineer Location: Irvine CA (Onsite Position ...
5 days ago
... in System Verilog and UVM verification methodologyExperience with Linux operating systemExperience ... with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps ...
19 days ago
Description: Trident Consulting is seeking a " Principal Optical Design Engineer for one of our ... and technology services. Role: Principal Optical Design Engineer Location: San Jose, CA ...
28 days ago
... Description: Job Title: Systems Safety Engineer Location: San Diego, CA About ... We are seeking a Senior Principal Systems Safety Engineer to join our team ...
19 days ago
... Engineer Location: Santa Clara, CA, 95051 Duration:12 Months Job Description: Principal ...
14 days ago
... outstanding Camera Image Quality Test Engineer who has a good understanding of ... and real world image quality verification to help deliver the best ...
15 days ago
Description: 1.Good in SolidWorks (1 to 2 years) 2.Windchill Change management experience 3.Medical Device Product development 4.Validation & Verification (V&V) 5. Good in communication and interpersonal skills
20 days ago
Description: As aLead Package Design Engineer, you will take ownership of ... for manufacturing, and sign-off verification. You will also , guiding best ...
20 days ago
... for a Staff level Embedded Software Engineer to join our team, focusing ... the software stack for Design Verification of PCBAs & ECUs (Electronic Component ...
21 days ago
... for a Staff level Embedded Software Engineer to join our team, focusing ... the software stack for Design Verification of PCBAs & ECUs (Electronic Component ...
21 days ago
... comprehensive testing schedules for Design Verification (DV) and Validation activities, collaborating ... within project managem The Project Engineer will be a key member of ...
28 days ago
... /Requirements: Provide successful validation and verification of Applications (ERP and packaged ...
29 days ago