Description: Role: Silicon Design Package Engineer Location: Hybrid (Santa Clara, CA ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ...
22 days ago
... , Full Time / Permanent Role Role: Design Verification Engineer Location : Sunnyvale CA / Austin ...
22 hours ago
Description: Role: Design Verification Engineer Location: San Jose CA/ Irvine ...
14 days ago
... ! We are looking for a Design Verification Engineer to join our growing team ...
29 days ago
Description: Engineer the Future-One Optimization at a Time Step into a high- ... , and design. This opportunity is ideal for a mid-level CAE professional who ... thrives at the intersection of simulation, optimization, and ...
28 days ago
Description: Cohesive Technologies is a global IT Services & Solutions company providing IT Staffing Services and Application Development Services necessary for technology leaders to deliver business value. We help our people and clients succeed by ...
28 days ago
Description: Job Title:DesignVerificationEngineerLocation:San Diego, CAExperience Level: 7+ YearsJob Description:We are seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ...
4 days ago
... Medical Device Quality Engineer / Senior Sustaining Quality Engineer Needed for Growing Medical ... for a talented Senior Design Quality Engineer / Senior Supplier Quality Engineer! Why join us ...
6 days ago
... Medical Device Quality Engineer / Senior Sustaining Quality Engineer Needed for Growing Medical ... for a talented Senior Design Quality Engineer / Senior Supplier Quality Engineer! Why join us ...
21 days ago
... Medical Device Quality Engineer / Senior Sustaining Quality Engineer Needed for Growing Medical ... for a talented Senior Design Quality Engineer / Senior Supplier Quality Engineer! Why join us ...
a month ago
... Power Engineer DUTIES ASIC Power Engineer to perform power analysis and optimizations in ... and SystemVerilog. RESPONSIBILITIES Perform PPA optimization with Fusion compiler. Perform RTL ...
8 days ago
Description: Role: Network Support Engineer Location Santa Clara, CA - ... Carrier Interconnect Optimization Hybrid DC Network Architecture & Fabric Design Job Description/Responsibilities ... focused on the architecture, design, development and deployment of ...
27 days ago
... Description Thermal Design: Heatsink topology, vapor chambers, heat pipes, fin optimization; fan ...
8 days ago
Description: Role: ASIC Power Engineer Location: Sunnyvale, CA (Hybrid) DUTIES: ... ASIC Power Engineer to perform power analysis and optimizations in ASIC for ... and SystemVerilog. RESPONSIBILITIES: Perform PPA optimization with Fusion compiler. Perform RTL ...
8 days ago
... are hiring a Senior Embedded Software Engineer to start immediately. This is ... Software Engineer belonging to the Enterprise Engineering Department to lead the design ... , development, and optimization of embedded software solutions ...
28 days ago
... company building advanced analytics and optimization platforms for complex, large-scale ... . As a Senior Data Platform Engineer, you will design and scale the core ...
14 days ago
Description: Job Description Design, develop, troubleshoot and debug software ... possible, with increase emphasis on optimization and AI integration. You will ...
30 days ago
... : Job ID: 65213 Senior Server Engineer Location: 55 Trinity Avenue, Suite ... Senior Server Engineer (Contract) will lead engineering, troubleshooting, and optimization of enterprise ...
6 days ago
... trying to source Sr. Network Engineer for our direct client for ... Engineer is responsible for the planning, development, installation, configuration, maintenance, and optimization ...
29 days ago
... complex challenges in machine learning, optimization, and distributed systems to power ...
2 days ago