Description: Role: RTL Design Engineer Location: Santa Clara, CA ... -on experience in digital design at the RTL level using Verilog/SystemVerilog ... . Experience in designing and implementing RTL from scratch. Proficiency in applying ...
16 days ago
... defined features/escalations Create updated RTL design for identified issues and block ...
21 days ago
... : Job Title: LLM & RTL Integration Engineer Locations: Bay Area ... source LLMs for RTL (Register Transfer Level) design. The ideal ... candidate will work closely with RTL domain ... and optimize AI-assisted RTL integration workflows. The role ...
15 days ago
... open-source LLMs for RTL (Register Transfer Level) design. The ideal candidate ... will work closely with RTL domain experts ... develop and optimize AI-assisted RTL integration workflows. The role involves ...
18 days ago
$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, ... : Good knowledge of System-Verilog RTL coding including state machines, adders ... , etc. Good understanding of digital design for mixed signal control loops ...
17 days ago
... custom pipelines for LLM-assisted RTL design, analysis, and verification.Work with ... RTL experts to fine-tune prompts ... performance.Prompt Engineering and Optimization: Design, refine, and test
22 days ago
... Description: LLM Engineer AI-Assisted RTL Integration Location: Bay Area, ... source LLMs for RTL (Register Transfer Level) design. The ideal ... candidate will work closely with RTL domain ... and optimize AI-assisted RTL integration workflows. The ...
18 days ago
... Description: LLM Engineer AI-Assisted RTL Integration Location: Bay Area, ... source LLMs for RTL (Register Transfer Level) design. The ideal ... candidate will work closely with RTL domain ... and optimize AI-assisted RTL integration workflows. The ...
22 days ago
... open-source LLMs for RTL (Register Transfer Level) design. The ideal candidate ... will work closely with RTL domain experts ... develop and optimize AI-assisted RTL integration workflows.The role involves ...
15 days ago
... open-source LLMs for RTL (Register Transfer Level) design. The ideal candidate ... will work closely with RTL domain experts ... develop and optimize AI-assisted RTL integration workflows.The role involves ...
18 days ago
... : Strong knowledge of System-Verilog RTL coding, including state machines, adders ... logic. Solid understanding of digital design for mixed-signal control loops ...
16 days ago