Description: Job Title: Design Verification Engineer Duration: Full time or Contract ... to-end solutions for ASIC/FPGA Design both in Digital/Analog ... Design & Implementation, Functional Verification, Physical Design, AMS Verification, Layout Design, and circuit ...
27 days ago
Description: Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) ... and implement IP/SoC verification plans, build verification test benches to enable ... tests based on verification test plan Drive Design Verification to closure based ...
6 hours ago
Description: Role: Design Verification Engineer Location: Bay Area, CA Hybrid ... Key Responsibilities: * Develop and implement verification plans for complex SoC designs ... using SystemVerilog and UVM (Universal Verification Methodology). * Write and execute ...
22 days ago
Description: Role: Design verification EngineerLocation: Sunnyvale or Austin, USADesign Verification Engineering ServicesTestbench development ...
22 days ago