... Description: Job Title: Senior ASIC Design Engineer Location:San Jose ,CA Contract: ... : Technical: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to ... to also do block level RTL design or block or top- ...
22 hours ago
Description: Job Title: Senior ASIC Design Engineer Location: San Jose, CA What ... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ... to engage in block-level RTL design or block or top-level ...
15 days ago