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Jobs and careers for system debug lead engineer in California (3 jobs)

Design verification engineer
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Design Verification Engineer

  • Sivaltech
  • San Diego
... seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies ... theverificationenvironment.Responsibilities:Develop, enhance, and debug System Veri
5 days ago

Design Verification Engineer

  • Mirafra Inc
  • San Jose
Description: Role: Design Verification Engineer Location: San Jose CA/ Irvine ... mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans ... -level tests in C,SV,UVM Debug RTL and Gate simula
14 days ago

Design Verification Engineer

  • Reveille Technologies
  • Sunnyvale
... / Permanent Role Role: Design Verification Engineer Location : Sunnyvale CA / Austin TX ... good debugging skills. Build UVM/System Verilog-based verification environments for ...
a day ago

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