... seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies ... theverificationenvironment.Responsibilities:Develop, enhance, and debug System Veri
4 days ago
Description: Role: Design Verification Engineer Location: San Jose CA/ Irvine ... mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans ... -level tests in C,SV,UVM Debug RTL and Gate simula
14 days ago
... / Permanent Role Role: Design Verification Engineer Location : Sunnyvale CA / Austin TX ... good debugging skills. Build UVM/System Verilog-based verification environments for ...
22 hours ago