Description: Job Title: Senior FPGA/RTL Design Engineer Location: Remote Contract: 12+ Months What You'll Be Doing: Strong expertise on Arteris Design Toolset At-least 5+ years of experience in Verilog Design AMBA AXI bus along-with ARM or C based ...
2 days ago
Description: FPGA Verification Engineer Santa Clara, CAMandatory Areas Must Have Skills Skill 1 - 8 + Years of in FPGA Skill 2 - 5 +Years of Exp in UVM Skill 2 - 5 +Years of Exp in System VerlilogJob Description: We are seeking a highly motivated and ...
15 days ago