Description: Senior Machine Learning Software ... highly skilled and experienced Senior Machine Learning Software Engineer ... Augmented Generation (RAG) systems, and Agentic systems. This role involves ... machine learning models and systems to address real-world ...
11 days ago
$59
$69
an hour
... has a client that is seeking a Senior Designer in Mountain View, CA ... . Summary: We are seeking a seasoned Senior User Experience (UX) Designer to ... in analyzing business processes and systems to drive improvements and implement ...
17 days ago
Description: Senior Machine Learning Software ... highly skilled and experienced Senior Machine Learning Software Engineer ... Augmented Generation (RAG) systems, and Agentic systems. This role involves ... machine learning models and systems to address real-world ...
a month ago
Description: Job Title: Senior Design Verification Engineer Location: Mountainview, ... -least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI ...
24 days ago
... SDV solutions, including drivers, operating system, BSP and software stack. We ...
23 days ago
Description: Job Description Hybrid: This means the successful candidate is expected to report to their primary location (Mountain View, California) three times per week, at minimum. Relocation: This job may be eligible for relocation benefits The Role: ...
15 days ago
... company is looking for a Mid-Senior level QA Engineer to join ... experience in mobile device testing (Android/iOS), API testing, and a passion for ...
23 days ago
... Validation/Test Automation Automated hardware testing. Writing automation software targeting automated ... engineer with significant Python experience. Testing system level hardware kits that go ...
24 days ago
... design, development, testing, and evaluation of the software and systems that make ... , designs, develops and tests operating systems-level software, compilers, and network ...
a day ago
... -least 5+ years of experience in System Verilog HVL and C/C++. AMBA AXI ... in test bench, stress/corner testing, failure debug, gate level simulations ...
11 days ago
... UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing ...
14 days ago
... UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing ...
22 days ago
... UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing ...
27 days ago
... group is responsible for safeguarding systems, networks, and data from evolving ... layer. We're looking for a Senior Application Security Engineer to help ...
5 hours ago