Description: Verification Engineer Location - Bay Area, CA Type: ... : A MINIMUM of 8-15 years in ASIC verification in the area of ... /UVM) with a strong understanding of ASIC Design and Verification flow. Experience with ...
23 hours ago
Description: CoWoS Packaging Engineer Location - Bay Area, CA - Candidate ... a skilled and motivated CoWoS Packaging Engineer to join our growing team ... applications. You will collaborate with design, process, manufacturing, and materials teams ...
8 days ago
... a skilled and motivated CoWoS Packaging Engineer to join our growing team ... applications. You will collaborate with design, process, manufacturing, and materials teams ...
11 days ago