Description: Role: Design Verification Engineer Location: Bay Area, CA ... : * Develop and implement verification plans for complex SoC designs, with a focus on ... using SystemVerilog and UVM (Universal Verification Methodology). * Write and execute test ...
18 days ago
... for LLM-assisted RTL design, analysis, and verification.Work with RTL experts ... performance.Prompt Engineering and Optimization: Design, refine, and test
a day ago
... will contribute to the design, development, and verification of software that interacts ...
23 days ago