... Description: Job Title: Senior ASIC Design Engineer Location:San Jose ,CA Contract: ... : Technical: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to ... also do block level RTL design or block or top- ...
a day ago
... experience High-speed layout design, High density PCB design, Cadence Allegro 16.x ... will Be Doing: Expert in PCB design tools Cadence Allegro 16.x ... experience in high density PCB design up to 28 layers ... high-speed layout design requirements Working knowledge
5 days ago
Description: Job Title: Hardware Validation Engineer Location: San Mateo, CA (Complete ... are seeking a driven and versatile engineer to help drive safety and ... test plans that enable rapid design iteration and robust product validation ...
2 days ago