Description: Job Title: Senior ASIC Design Engineer Location:San Jose ,CA Contract: ... fullchip SDCs and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
23 hours ago
Description: Job Title: Hardware Validation Engineer Location: San Mateo, CA (Complete ... are seeking a driven and versatile engineer to help drive safety and ... test plans that enable rapid design iteration and robust product validation ...
2 days ago