Description: Position: Physical Design Engineer Location: San Jose CA (Day-1 Onsite) Long Term Contract Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus ...
14 days ago
Description: Position: Senior ASIC Design Engineer Emulation(HAPS Engineer) Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating ...
26 days ago