Description: Role: Mixed-Signal Verification Engineer Location: San Jose, CA 100% ... : Contract Qualifications: Strong knowledge of System-Verilog RTL coding, including state ...
20 days ago
Description: Role: Post-Silicon Validation Engineer Location: San Jose, CA Hybrid ... manufacturing concepts. Proficiency in low-level C, C++, RISC-V assembler, microcoding, Python, and ...
20 days ago