Description: Role: Post-Silicon Validation Engineer Location: San Jose, CA Hybrid ... manufacturing concepts. Proficiency in low-level C, C++, RISC-V assembler, microcoding, Python, and ...
17 days ago
Description: Role: Mixed-Signal Verification Engineer Location: San Jose, CA 100% ... mixed-signal control loops and experience writing Verilog/Verilog-A code to ...
17 days ago