Description: Role: Post-Silicon Validation Engineer Location: San Jose, CA Hybrid ... of IC design, Design for Test (DFT), and manufacturing concepts. Proficiency ...
27 days ago
... Power Integrity (SI/PI) Design Engineer Location: San Jose, CA 100 ... Type: Contract SI/PI Design Engineer Responsibilities: Lead chip-package-system ... , netlists, and methodologies for High-Performance Computing using 2.5D/3D package ...
27 days ago