Description: PSV PCIE Validation & Emulation Engineer Experience: 5 to 8 years Salary Range: ... : Create and document PCIe validation test plans, test cases, and scripts. Perform ...
a day ago
... Title: Power & Performance (PnP) Validation Engineer Location: San Jose, CA Company ... lab tools.Develop testbenches and test cases for RTL/firmware verification ...
a day ago
Description: Job Title: SoC Lead Engineer Location: San Jose, CA Company: ... .Collaborate with verification teams for test planning and RTL simulation/debug ...
7 days ago
Description: PSV Memory Validation & Emulation Engineer Experience: 5 to 8 years Salary Range: ...
a day ago
Description: Physical Design Engineer Contract First preference : CA Second ...
7 days ago
Description: Job Title: FPGA Engineer Location: San Jose, CA, USA ...
8 days ago
Description: Position: 1- Firmware Engineer C, C++ microcontrollers, UART, I2C, SPI, USB, ... Development, Hardware Integration. position: 2- Validation Engineer VHDL, Verilog, Hardware Description Languages ...
13 days ago