Description:
Physical Design Engineer Contract First preference : CA Second preference: Anywhere in the US Expected Start Date: 1st week of June Client: TESSOLVE Mandatory Skills/Experience Experience in leading and executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience in understanding and writing synthesis design constraints for hierarchical physical partitions Experience in STA and Timing closure for very high-speed designs > 1 GHz Experience with TSMC 12FFC node and other FINFE
May 13, 2025;
from:
dice.com