Where

Physical Design Engineer ( Full-chip Hierarchical Physical Design of Mixed-signal chips)

Wise Equation Solutions Inc.
San Jose Full-day Temporary

Description:

Physical Design Engineer Long term Contract First preference : San Jose, CA ( Onsite) Mandatory Skills/Experience Experience in leading and executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience in understanding and writing synthesis design constraints for hierarchical physical partitions Experience in STA and Timing closure for very high-speed designs > 1 GHz Experience with TSMC 12FFC node and other FINFET nodes (desirable) Experience with Synopsys ICC2 based P&R f
May 29, 2025;   from: dice.com

Similar jobs

Description: Minimum Qualifications Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience Experience with ...
12 hours ago
Description: Position: Senior ASIC Design Engineer- Emulation (HAPS Engineer) Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating ...
14 days ago
  • VIVA USA INC
  • San Jose
Description: Title: DFX RTL Design Engineer - Hybrid Mandatory skills: RTL, RTL design, RTL checks, RTL coding, RTL implementation, Gbit SERDES, UCIe, PCIe I/F, DFX RTL coding, DFX RTL integration, Verilog, system verilog, lint, elab, CDC, RDC, SOC, JTAG, ...
22 days ago
  • Recruitment.ai
  • San Jose
Description: Job DescriptionDesign high speed PCBsPerform schematic and board level reviews.Bring up PCBs and systems using diagnostic software.Perform unit level validation of boards and systems following published guidelines and a test plan.Debug ...
14 days ago