Physical Design Engineer ( Full-chip Hierarchical Physical Design of Mixed-signal chips)

Description:

Physical Design Engineer Long term Contract First preference : San Jose, CA ( Onsite) Mandatory Skills/Experience Experience in leading and executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience in understanding and writing synthesis design constraints for hierarchical physical partitions Experience in STA and Timing closure for very high-speed designs > 1 GHz Experience with TSMC 12FFC node and other FINFET nodes (desirable) Experience with Synopsys ICC2 based P&R f